1. Field of the Invention
The present invention relates to a digital phase detector and, more particularly, to a digital phase detector which is fabricated in a standard digital CMOS process and is used as a phase comparator in a Phase-Locked Loop (PLL) circuit.
2. Description of the Related Art
In a conventional analog PLL circuit, phase difference information from a phase comparator is given in the form of an output pulse width, and a charge pump circuit supplies a charge proportional to the pulse width to a control voltage terminal of a voltage-controlled oscillator (VCO). A loop filter, to which the control voltage terminal is also connected, converts the charge supplied from the charge pump circuit into a voltage value.
An analog PLL circuit such as described above uses analog devices such as a capacitive device and a resistive device, but since such analog devices cannot be fabricated using a standard digital CMOS process, different options are often needed. Furthermore, in cases where these analog devices become a dominant factor in determining the area that the PLL circuit occupies, the benefits of the recent digital CMOS miniaturization cannot be taken advantage of. Moreover, the analog configuration has two or more poles in the loop of the PLL circuit; therefore, if the bandwidth of the loop is set wide, the phase margin is reduced and, as a result, it becomes difficult to reduce the response time of the PLL circuit.
In view of the above situation, research and development of an all digital PLL (Phase-Locked Loop) circuit, in which all of the constituent elements are digital has been proceeding in recent years. To implement such an all digital PLL circuit, a digital phase comparator that outputs a phase difference in the form of a digital code becomes necessary in place of a phase comparator, such as used in an analog PLL circuit, which converts phase difference information into an output pulse time difference.
In the prior art, Japanese Unexamined Patent Publication (Kokai) No. 2002-076886 discloses a digital phase detector that is capable of accommodating a quantization scheme to measure delay differences between the edge of a VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital code for use by a frequency synthesizer.
Further, in the prior art, Japanese Patent No. 3143743 (corresponding to Japanese Unexamined Patent Publication (Kokai) No. 20002-029564) discloses, as a phase synchronization technique that can compensate for a delay time while reducing power consumption, a high-speed phase synchronization circuit which generates a measurement start signal and a measurement end signal by measuring the phase of a reference clock signal externally input by an enable signal and the phase of its feedback clock signal, outputs a delay time compensating cycle determining signal for each measured delay unit by using the two signals, generates a delay time compensating signal in accordance with the delay time compensating cycle determining signal, and outputs a phase-synchronized clock signal by delaying the reference clock signal.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.